Learn VHDL and SystemVerilogby writing real code.
Learn VHDL and SystemVerilog
by writing real code.CodeWaveformNetlist
VHDLSVSystemVerilog
-- A 4-bit counter: counts up while en is highlibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity pulse_counter is port ( clk : in std_logic; rst : in std_logic; en : in std_logic; count : out std_logic_vector(3 downto 0) );end entity pulse_counter;architecture rtl of pulse_counter is signal count_r : unsigned(3 downto 0);begin -- One register and one adder: that's the -- whole design once it reaches silicon process (clk) is begin if rising_edge(clk) then if rst = '1' then count_r <= (others => '0'); elsif en = '1' then count_r <= count_r + 1; end if; end if; end process; count <= std_logic_vector(count_r);end architecture rtl;Write code, run simulations, see waveforms and netlists.
Start the free courseSolve a challenge
1
Write
Real VHDL or SystemVerilog in a full editor with instant syntax feedback.
2
Run
GHDL and Icarus simulate your design against a testbench; Yosys synthesizes it. All in seconds.
3
See
Explore interactive waveforms and a block diagram of what your code became. Click any block to see the code behind it.
106
Lessons
115
Live examples
111
Exercises
50
Challenges
Instant Feedback
Submit your code, get simulation results and synthesis reports in seconds. Fix, iterate, learn.
Live Waveforms
See your simulation results as interactive waveform diagrams, right in the browser.
Guided Curriculum
Structured lessons from basics to advanced, with challenges to test your understanding at every step.
Multi-Language
Write VHDL or SystemVerilog. Both run on the same real EDA toolchain.
Practice Challenges
Story-driven HDL challenges with real testbenches, free for everyone. Pick one and solve it in your browser.
No Setup Required
Skip the hours of tool installation and expensive licenses. Everything runs in your browser, ready in seconds.
Start learning. Start building.
Follow the course, jump into challenges, or bring your own code.
Learn
Structured courses from basics to advanced. Follow a guided path with lessons, examples, and instant feedback.
Digital FoundationsFreeThe entire Fundamentals level is free: lessons, exercises, and instant feedback.Explore full curriculum →
Practice
Challenges built to feel like real engineering work.
Archive Flash BurstadvancedIssue a SPI fast-read with its dummy phase intact and stream four bytes back under one chip selectBrowse all challenges →
Playground
Your own RTL, wild west. Paste any VHDL or SystemVerilog and run it. No account needed.
Open the playgroundFreeSimulate, synthesize, and explore waveforms and block diagrams of your own designs.Open playground →
“If someone goes through this course and does the practice problems, I would imagine they are easily able to pass most coding interviews for hardware design.”
\- Andrew, early user
Come build with us.
RisingEdge is built in the open with hardware engineers. Sign up free, no invite needed. Solve challenges, share your runs, and tell us what should come next.