GrieferPig/esp32-s31-linux
Porting MMU Linux to ESP32-S31. Contribute to GrieferPig/esp32-s31-linux development by creating an account on GitHub.
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README
Linux 6.12 for ESP32-S31 An attempt to port MMU Linux to S31's architecture (RV32IMAFBCNSUX). Module tested: ESP32-S31-WROOM-3 E1H16R16V (ESP32-S31 Core Board). Example boot log Build/Flash Instructions Refer to the Build Instructions. Porting progress General
Feature Status
Buildroot rootfs 🟡 Untested
Wireless (ESP-Hosted) 🟡 Untested
Reboot and poweroff 🟡 Untested
Dual hart SMP ⚫ Not Planned (Used by FreeRTOS)
Peripheral Drivers
Feature Status
AXI GDMA 🟡 Untested
AHB GDMA 🟡 Untested
Cache driver 🟡 Untested
TRNG 🟡 Untested
eFuse 🟡 Untested
Watchdog 🟡 Untested
PWM, counter, analog peripherals 🟡 Untested
CLIC/CLINT interrupt driver 🟡 Untested
Flash MTD driver 🟡 Untested
Timers 🟠 WIP
Clock tree 🟠 WIP
Security accelerators 🟠 WIP
LP subsystem & IPC 🔴 Not Implemented
PMP/APM 🔴 Not Implemented (properly)
Connectivity Drivers
Feature Status
UART0 console 🟡 Untested
UART1/2 🟡 Untested
GMAC Ethernet 🟡 Untested
SDMMC 🟡 Untested
GPIO 🟡 Untested
pinctrl/GPIO Matrix 🟡 Untested
USB 🟠 WIP
I2C 🔴 Not Implemented
I2S 🔴 Not Implemented
SPI 🔴 Not Implemented
RMT 🔴 Not Implemented
USB Serial/JTAG ⚫ Not Planned (Used by FreeRTOS)
🟢 Stable — Fully tested and working | 🟡 Untested — Seems working; not throughly tested | 🟠 WIP - Functions not fully implemented
Also check out these command outputs. S31 Quirks (For more hardware references, see docs/ folder) This port was done before S31 TRM is available, therefore these guessworks were made: CLIC v. PLIC v. CLINT S31 uses CLIC and CLINT similar to P4. Linux expects PLIC. Therefore a custom CLIC driver is needed. I referenced this CLIC patch from disdi to get the CLIC working. Also, standard RISC-V interrupt CSRs are not usable, presumably because, from P4's TRM, CLINT interrupts are routed to CLIC and mtvec.MODE is hardwired to 0x3 (CLIC mode). Patches needed to make OpenSBI interrupts work. S mode S31's supervisor mode is not standard and has absolutely no usage in ESP-IDF so a lot of these CSR uses were mostly guessed from either P4's TRM or CSR probing (see docs/). For example, the use of sclicbase(?) and the lack of sie. S31 implemented SCLIC (Supervisor CLIC?) which is confusing since there is no known standardization; According to all laws of esp-idf, mcliccfg.NMBITS is not writable. IT IS WRITABLE! And setting it to 0b01 enables writes to the clicintattr[i].MODE field and thus enabling the use of S-mode interrupts. OpenSBI and Linux XIP To save the precious 16MB PSRAM memory, OpenSBI was modified to use XIP in flash and internal SRAM (hence the 3915901 KB firmware size in OpenSBI banner, since flash and SRAM mappings are not continuous). In mainline linux, XIP support on RISC-V was removed, so 6.12 was used instead which has proper XIP support. Appendix (as of 7/21/26) ~ # coremark 2K performance run parameters for coremark. CoreMark Size : 666 Total ticks : 18887 Total time (secs): 18.887000 Iterations/Sec : 1058.929422 Iterations : 20000 Compiler version : GCC15.2.0 Compiler flags : -O2 -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -O2 -g0 Memory location : Please put data memory location here (e.g. code in flash, data on heap etc) seedcrc : 0xe9f5 [0]crclist : 0xe714 [0]crcmatrix : 0x1fd7 [0]crcstate : 0x8e3a [0]crcfinal : 0x382f Correct operation validated. See README.md for run and reporting rules. CoreMark 1.0 : 1058.929422 / GCC15.2.0 -O2 -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -O2 -g0 / Heap